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Fathimath Luludha O V is a Design Verification Engineer at SeviTech Systems Pvt. Ltd. since October 2021, with prior experience as a VLSI Design and Verification trainee at Maven Silicon. Fathimath has expertise in Verilog, System Verilog HVL, System Verilog assertion, and UVM, and previously worked as a Hardware Engineer at Mindteck, where responsibility included the end-to-end electronic hardware development cycle and the design of various electronic devices. Fathimath possesses skills in using laboratory tools and test equipment and has participated in internal audits of quality management systems. Fathimath holds a Bachelor of Technology degree in Electronics and Communications Engineering from the College of Engineering Trivandrum.