The Design Verification Engineers at SeviTech Systems Pvt. Ltd. are responsible for ensuring the functionality and performance of ASIC and FPGA designs before fabrication. They utilize various verification methodologies, including formal verification and simulation, to identify and rectify design flaws, thereby guaranteeing that the final product meets specified requirements. This team collaborates closely with design engineers to validate complex digital and mixed-signal circuits, ensuring high-quality outcomes in semiconductor projects, from RTL to GDS.
Ajeet Kadam
Design Verification Engineer
Brahmam Esojipeta
Design Verification Engineer
Kaneez e Zehra
Design Verification Engineer
Mallikarjuna N
Design Verification Engineer
Raghu Krishna
Senior Verification Engineer
Rajeshwari N.
Verification Engineer
Renjith Lal C P
Senior Design Verification Eng...
Sivaprasad Kolakutla
Design Verification Engineer
Srihari V S
Design Verification Engineer
Suneet Garg
Verification Lead
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