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Shreevidya V is a Lead Engineer at LeadSoc Technologies Pvt Ltd since August 2024, following experience as a Senior Engineer at Insemi Technology Services Pvt. Ltd. from May 2023 to July 2024, where involvement included a 7nm project encompassing ispatial synthesis to GDSII signoff checks. Prior experience includes roles as a Senior Physical Design Engineer at Sankalp Semiconductor from August 2018 to November 2022, focusing on block-level PNR implementation, and as a Senior PCB Design Engineer at UST Global from January 2017 to January 2018. Additionally, Shreevidya worked as a PCB Design Engineer at VVDN Technologies from August 2014 to December 2016 and as a PCB Designer at Micro Cad Services from March 2011 to December 2013. Shreevidya V holds a Bachelor of Engineering degree in Electrical and Electronics Engineering from Visvesvaraya Technological University, completed in 2010.