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Canberk Topal is a Senior Digital Design Engineer at Riverlane since January 2023, focusing on implementing Quantum Error Correction algorithms on hardware. Prior to this, Canberk worked at lowRISC CIC from July 2021 to January 2023 as a Hardware/Software Engineer, contributing to the OpenTitan project with design verification tasks for various processors, including OTBN and Ibex. Earlier experience includes a role as a Graduate Hardware/Software Engineer at Dialog Semiconductor, where responsibilities involved RTL design and supporting front-end signoff activities for Power Management ICs. Canberk's internship experiences at HAVELSAN and Aselsan involved projects related to 5G technology and military communication protocols, respectively. Canberk holds a Bachelor of Science degree in Electrical, Electronics and Communications Engineering from Istanbul Technical University, completed in 2020.