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Venkateshwara Rao has worked in the semiconductor industry for over a decade. In 2008, they began their career as an Intern at NVIDIA. In 2009, they moved to Vitesse Semiconductor as a Design Engineer, where they worked on the verification of 10G phy and developed OVM based testbench. In 2010, they returned to NVIDIA as an ASIC Design Engineer, where they worked on developing testbench for a co processor cluster and developed testcase infrastructure to re-use the tests written at cluster level. In 2017, they joined Cisco as a Senior Hardware Engineer, where they worked on the verification of block level testbench and used fully constrained random stimulus generation. Most recently, in 2019, they joined Kinara, Inc. as a Verification Manager, where they worked on creating different block level and chip level testbenches from scratch, created scalable test infrastructure to run tests from verification to silicon, and worked on silicon bring up activities and silicon validation.

Venkateshwara Rao attended the International Institute of Information Technology from 2007 to 2009, where they earned a M.Tech degree in VLSI & EMBEDDED SYSTEMS.