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Dvor Efrat is a highly experienced professional in the field of VLSI and ASIC design, currently serving as a Senior Principal Application Engineer at Cadence Design Systems since September 2022, where expertise in full chip flow and customer support is provided. With over eight years as VLSI Manager at Valens, Dvor manages a team of around 50 engineers, overseeing design, verification, implementation, and prototyping for various products, while also leading automotive project management efforts. Previous roles include Chip Architect and Senior Project Manager at DSP Group, where oversight of ASIC projects and design specifications was conducted, as well as experience at Infineon and Runcom in ASIC implementation and VLSI design. Dvor holds an M.B.A. from the Technion - Israel Institute of Technology and a B.Sc. in Electrical Engineering and Computer Science from Tel Aviv University.