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Srinivasulu Pola has held various roles and gained experience in the field of VLSI design and implementation. In 2010, they worked as a Graduate Assistant at Polytechnic Institute of New York University, assisting administrative assistants and orienting international students. In 2011, they continued as a Graduate Assistant and was responsible for VLSI design and implementation of high-speed crossbars in 32nm technology, as well as analyzing and evaluating multi-core interconnection. From 2012 onwards, they joined Arasan Chip Systems Inc. as a Design Engineer, where they were responsible for developing static time constraints, synthesis, power and area optimization, and scan chain insertion for various technologies including MIPI M-PHY and USB2.0 PHY. Srinivasulu also performed timing sign-off (STA) and power analysis, along with back-annotated SDF simulations. Additionally, they had a brief internship as a Design Engineering Intern at Arasan Chip Systems Inc. in 2012.

Srinivasulu Pola obtained a Master's degree in Electrical Engineering from the Polytechnic Institute of New York University from 2010 to 2012. Prior to that, they completed their Bachelor's degree in Electronics and Communication Engineering from Visvesvaraya Technological University from 2005 to 2009. Srinivasulu then pursued a certification in VLSI Engineering from UCSC Extension Silicon Valley, from 2012 onwards. Additionally, Srinivasulu Pola obtained a certification in Computer Engineering from the Polytechnic Institute of New York University in January 2010.