ÂÜÀòÂÒÂ×

Balaji Sathyanarayanan is a Principal Engineer at Western Digital since April 2020, bringing extensive experience from previous roles at Samsung Electronics, where a significant contribution was made as a Staff Engineer, Technical Lead, and Design Engineer from November 2010 to March 2020, including the successful RTL designs for four memory products currently in mass production and the design of DMA blocks in eMMC and uSD card controllers. Prior experience includes a Design Engineer position at Sasken Communication Technologies Ltd, where work on RTL verification for OMAP3430 was conducted as a contractor for Texas Instruments, India. Balaji holds a Master of Science in System On Chip Design from Lund University and a Bachelor of Engineering in Electronics from B. M. S. College of Engineering. Academic foundations were built at Vijaya PU College and SSVM.