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Stefan Stojicic started their work experience as a Junior Verification Engineer at HDL Design House in March 2021 and worked until November 2022. Stefan then joined Veriest as a Verification Engineer starting in December 2022.

Stefan Stojicic has a diverse education history in the field of Electrical Engineering and Computer Science. Stefan obtained their Master's degree in Electrical Engineering and Computer Science with a specialization in Information and Communication Technologies from the University of Belgrade, School of Electrical Engineering. Stefan completed this degree from 2021 to 2023.

Prior to their Master's degree, Stefan Stojicic earned their Bachelor's degree in Electrical Engineering and Computer Science from the same institution. Stefan studied Telecommunications and Information Technology during their undergraduate studies, which took place from 2015 to 2021.

Before attending university, Stefan Stojicic obtained their High School Diploma from The Zemun Gymnasium. Stefan'sfield of study during their high school years was Natural Science and Mathematics, and they completed their diploma from 2011 to 2015.

In addition to their formal education, Stefan Stojicic has acquired several certifications. Notably, they passed the exams for SystemVerilog Accelerated Verification with UVM v1.2.5, SystemVerilog Assertions v5.1, JasperGold Connectivity App v21.06, Jaspergold Formal Expert v21.06, SVA, Formal and Jaspergold Fundamentals for Designers v19.03, SystemVerilog Assertions v4.2, and IoT Fundamentals: IoT Security. Stefan obtained these certifications from Cadence Design Systems and Cisco Networking Academy between 2021 and 2022.