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Srdjan Stojanovic

Design Verification Engineer at Veriest

Srdjan Stojanovic has worked as a Design Verification Engineer at Veriest since April 2020. Prior to that, they held the same role at ELSYS Eastern Europe from May 2015 to April 2020, at Frobas d.o.o. from November 2012 to April 2015, and at HDL Design House from November 2005 to September 2009. Srdjan also worked as a Software Developer at Schneider Electric DMS NS from October 2009 to October 2012.

Srdjan Stojanovic completed their Master's degree in Computer Engineering from the Faculty of Technical Sciences at the University of Novi Sad. Srdjan began their studies in 2000 and successfully completed them in 2006.

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