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Amit Pal is a skilled design engineer with extensive experience in ASIC IP and SOC verification. Currently serving as a Senior Design Engineer 2 at Tessolve since July 2020, Amit has previously held positions as a Design Verification Engineer at Test and Verification Solutions and as a VLSI front-end trainee at Maven Silicon. Prior to entering the industry, Amit contributed to academia as an Assistant Professor at Radharam Institute of Research and Technology and worked as a Radio Frequency Engineer at Sineone Teleservices Pvt. Ltd. Amit holds a Master of Technology in Digital Communications from Radharaman Institute of Technology & Science and a Bachelor of Technology in Electronics and Communication Engineering from All Saint College of Technology, further showcasing a strong educational foundation.