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Saiteja P is a Senior Physical Design Engineer at Synopsys Inc, with prior experience as an Engineer II at Qualcomm and an Engineer II in Physical Design at SmartSoC Solutions Pvt Ltd. At SmartSoC, significant contributions include working on 2.5M instance critical graphics tiles for AMD clients and developing an innovative graphical user interface for managing tiles. Earlier experience includes the implementation of Place and Route (PnR) for 5nm, automating issues using TCL scripts, and leading a team to develop an automatic presentation tool for PnR data assessment using Python. Saiteja P holds a Bachelor of Technology degree in Electronics and Communications Engineering from SRM University and completed education at the Birla Institute of Technology and Science, Pilani, along with Narayana Institute and Gowtham Model School for higher secondary and secondary education, respectively.