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Manjunath M is a seasoned Lead Engineer at Aricent since August 2018, with a significant background as a Senior Engineer at SmartPlay Technologies from April 2015 to present, specializing in Design Verification Engineering. Expertise includes IP and SoC verification using methodologies such as UVM and OVM, with proficiency in languages such as Verilog, System Verilog, and C/C++. Manjunath M possesses a comprehensive knowledge of various protocols, including DMA, Processor Verification, and Intel's specific protocols. Earlier experience includes serving as a Member Technical Staff at HCL Technologies from June 2011 to April 2015, focusing on System Verilog and SOC. Manjunath M holds a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from East Point College Of Engineering And Technology, completed in 2011.