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Prem Ranjan is an experienced FPGA design and validation engineer currently employed at SeviTech Systems Pvt. Ltd. since February 2022. Prior to this role, Prem served as an FPGA Design Engineer at Altran from November 2018 to February 2022, and at Indus Teqsite Private Limited (Datapatterns) from August 2017 to November 2018. Prem has a solid background in FPGA design, contributing to projects across multiple companies in the technology sector.