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Shrayansh Gupta is a Design Engineer currently working at Cadence Design Systems since May 2024, focusing on PDK/QA flow development and supporting PCells for design. Previously, Shrayansh worked at Texas Instruments as a Pcell Designer, contributing to advanced technology development projects and supporting designers with ESD, BICMOS, MOS, and DIODES PCELLs. Additionally, Shrayansh served as Design Engineer 1 at Tessolve, providing layout and automation support for PCELLs and layouts in research and development for Texas Instruments. Prior roles include positions at HCL Technologies and Intel Corporation, where Shrayansh worked as a PDK QA Engineer and Design Automation Engineer, respectively, focusing on PDK validation and testing. Shrayansh began a career in the industry with training at PinE Training Academy and holds a B.Tech in Electronics and Communications Engineering from Raj Kumar Goel Institute of Technology, graduated in 2021.