ÂÜÀòÂÒÂ×

HARSHINI VIJETHA H is a Senior Engineer I specializing in layout engineering and analog and mixed signal design at Sankalp Semiconductor, with a tenure beginning in October 2017. Prior to this role, HARSHINI completed a student internship at Aricent from February to May 2017. HARSHINI holds a Master of Technology (MTech) in VLSI Design and Embedded Systems from S J B Institute of Technology, completed in 2017, and a Bachelor of Engineering (BE) in Electronics and Communication Engineering from Sai Vidya Institute of Technology, earned in 2015.