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Philippe Legros has extensive work experience in the field of FPGA/ASIC design and management. Philippe started their career at Philips Semiconductors as an ASIC Designer from 1996 to 1997. Philippe then joined PLDA in 1998 and held various positions including Designer, Project Manager, and FPGA/ASIC Design Team Manager. In these roles, they were responsible for designing high-speed bus IP controllers for FPGA and ASIC, managing design teams, providing on-site support and trainings to international customers, and presenting at conferences. In 2021, Philippe joined Rambus as a Sr Principal Engineer, focusing on PCIe 6.x IPs development and architecture for the next generation of controllers.

Philippe Legros earned a BSc in Micro-electronics from ESIEE-ESTE from 1993 to 1996. Philippe also obtained an MSc in Telecommunications and Electronics from Middlesex University from 1997 to 1998. In 2016 and 2017, they pursued a 200-hour Yoga teacher certification at Mark Stephens Yoga.