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Vinodh Reddy is a Senior Analog Design Engineer at Alphawave Semi since February 2021, specializing in analog IC design, particularly in designing Phase-Locked Loops (PLL) and high-speed circuits for SerDes. Prior to this role, Vinodh served as a Member of the Technical Staff at Terminus Circuits Pvt Ltd from August 2018 to February 2021 and completed an internship in RTL Design at Winglobal tek from August 2017 to January 2018. Vinodh holds a Master's degree in VLSI and Embedded Systems from PESIT-BSC (2016-2018) and a Bachelor of Engineering in Electronics and Communications Engineering from PESIT BSC (2012-2016).