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Veeraj Patil is an experienced professional in the technology sector, currently serving as a Managing Partner at Rising Japan Infra Mumbai since January 2020. Concurrently, Veeraj Patil holds the position of IP Design Engineer at Open-Silicon, Inc. since January 2016. Previous roles include System Design Engineer at Lattice Semiconductor from April 2013 to December 2015 and Software Engineer at iGATE Patni from December 2011 to August 2012, where Veeraj Patil worked in the storage domain with EMC’s Engineering Functional Team on SAN/NAS products, as well as various testing tasks. Veeraj Patil earned a Bachelor of Engineering in Electronics from VIT, Pune, between 2007 and 2011.