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Ranganayakulu Guptha K has extensive experience in ASIC design, currently serving as an ASIC Design Engineer II at Open-Silicon since August 2012, focusing on physical design and physical design verification to ensure timing convergence, as well as conducting IR analysis. Previously, Ranganayakulu Guptha K worked as a graduate intern at Intel from February 2012 to July 2012, where responsibilities included working on blocks in eco mode to achieve convergence for tape-out.