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Dharma Rao Barlanka is a Senior ASIC Design Engineer II at Open-Silicon, Inc. DHARMA RAO previously worked as a Physical Design Engineer at Soctronics and as a VLSI Physical Designer Trainee at VEDA IIT. DHARMA RAO graduated from Railway High School with a Bachelor of Technology in Electrical, Electronics, and Communications Engineering. Their expertise includes FloorPlanning, Placement, CTS, and Route.