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Archana Mishra has a diverse background in engineering and verification, beginning with an engineering role at Minda from 2004 to 2005. Afterward, Archana held the position of R&D Engineer at Synopsys from 2012 to 2014. Since June 2006, Archana has served as Verification Team Lead at nSys Design Systems, specializing in SPI4.2 and SATA protocols, as well as utilizing System Verilog, Verilog, and VHDL languages, alongside verification methodologies such as OVM and VMM.