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Roee Saroosi is a Senior Design Verification Engineer at NextSilicon since August 2021, with extensive experience in pre-silicon validation. Previously, Roee Saroosi served as Validation Team Manager at Intel Corporation from April 2010 to July 2021, leading a pre-silicon IP level validation team and overseeing verification processes for unit blocks and SOC integration. Earlier roles included Pre Silicon Verification Engineer focused on DFx verification and software QA at Rontal, where Roee Saroosi utilized SQL databases. Roee Saroosi holds a degree in Electrical Engineering from Ben-Gurion University of the Negev, completed in 2009.