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Mike Hsieh is a seasoned engineer with extensive experience in ASIC design and engineering. Currently serving as a Principal ASIC Design Engineer at Netlist since October 2020, Mike has previously held significant roles at Intel Corporation as a Component Design Engineer, and at QLogic Corp. as a Principal Engineer, where responsibilities included engineering high-speed ASICs. Earlier career experiences include positions at LSI Logic as a design and staff engineer focusing on MPEG encoders, as well as an applications engineer at Xilinx. Mike began their professional journey at McDonnell Douglas as an Engineer Scientist Specialist. Mike Hsieh holds a Bachelor of Science degree in Electrical Engineering from UC Irvine, obtained between 1981 and 1985.