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Jianwei Li is a Senior ASIC Design Manager at Montage Technology, Inc., having held the position since August 2013. Responsibilities include managing the digital team and overseeing full chip architecture design, notably for the DDR5 RCD03 project at 6800, which has been sampled to customers. Prior experience includes serving as an ASIC Design Manager from 2009 to 2011, during which Jianwei Li worked on DDR3 register buffer and DDR3 load reduce buffer projects that achieved mass production at 2400. Earlier, Jianwei Li was an AISC designer at Hiview from April 2007 to August 2009, contributing to the Motion Compensation of the MPEG2 Decoder project. Jianwei Li holds a Master's degree in Navigation, Guide & Control from Harbin Engineering University.