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Chi-Yu Mao is a seasoned software engineer with extensive experience in the semiconductor industry, currently serving as a Principal Software Engineer at Lattice Semiconductor since December 2019, focusing on developing a new Analytical Placement engine for medium-sized FPGAs. Prior to this role, Chi-Yu worked as a Staff Software Engineer at Arm, developing standard cell validation tools, and held the position of Principal Engineer at Oracle, where contributions included the development of relative placement tools for microprocessor designs. Earlier career highlights include serving as an Architect at Chroma Design Automation, leading the development of next-generation floor planning tools, and as a Staff Engineer at Synopsys Inc, focusing on FPGA physical synthesis. Academic credentials include a Ph.D. in Electrical and Computer Engineering from the University of Wisconsin-Madison and both a Master’s and Bachelor’s degree in Electrical Engineering from National Chengkung University in Taiwan.