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Sahas Kumar Patha is a Digital Design Engineer at Kandou since June 2023, with extensive experience in ASIC design and digital engineering. Prior roles include Staff ASIC Design Engineer at MaxLinear from November 2021 to June 2023, and Senior Design Engineer 1 at Xilinx from August 2019 to November 2021. Sahas also served as a Senior ASIC Design Engineer and ASIC Design Engineer at MaxLinear between July 2015 and August 2019, and worked as a Research Student at the Indian Institute of Science, focusing on LTE-Advanced Cellular Systems. Earlier experience includes internships with Broadcom in 2013, specializing in Hardware Development, and CFTRI in Biochemistry. Sahas holds a Master of Engineering in Telecommunication Engineering from the Indian Institute of Science and a Bachelor of Engineering in Electronics and Communication Engineering from the Birla Institute of Technology and Science, Pilani.