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Triantafyllos Paidas is a junior verification engineer at HDL Design House since September 2020, specializing in ASIC System-on-chip design, verification, and embedded software development. Prior experience includes serving as an IT administrator with the Hellenic Army from October 2019 to July 2020 and working as a graphic and IT designer at Whale Graphics A.E. in 2018. Triantafyllos holds a Master's degree in Network Systems from Aristotle University of Thessaloniki, completed in 2019, and a Bachelor's degree from the University of Peloponnese, attained in 2017.