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Dawei Wang has a diverse work experience in the field of ASIC and FPGA design engineering. Dawei is currently working as a Sr. Principal ASIC Engineer at Fungible, Inc. since February 2020. Previously, they worked at Virtu Financial as a FPGA Acceleration Engineer from December 2018 to February 2020. Before that, they were an ASIC Design Engineer at Fungible, Inc. from April 2017 to November 2018.

From August 2012 to March 2017, Dawei worked at Juniper Networks as a Staff ASIC Design Engineer. In this role, they were responsible for writing Ethernet subsystem functional specifications, RTL development and implementation, as well as chip bring-up. Dawei successfully passed logic design for several tape-out ASICs during their tenure.

Prior to joining Juniper Networks, Dawei held the position of Senior Research Associate and Instructor at the Illinois Institute of Technology from November 2010 to July 2012.

Dawei Wang began their career as a Senior ASIC/FPGA Design Engineer at the Institute of Computing Technology, Chinese Academy of Sciences in July 2005. Dawei worked in this role until June 2009, and then rejoined the same organization from July 2009 to October 2010. Additionally, they served as an ASIC/FPGA Design Engineer from October 2005 to June 2008.

Dawei Wang completed their doctoral studies in Computer Architecture at the Institute of Computing Technology, Chinese Academy of Sciences from 2003 to 2009.