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Venkateshwara Rao has worked in various roles in the technology industry since 2008. From 2008-2009, they were an Intern at NVIDIA. From 2009-2010, they were a Design Engineer at Vitesse Semiconductor, where they worked on verification of 10G phy and developed OVM based testbench and verifying using OVM sequences. From 2010-2017, they were a Senior Hardware Engineer at NVIDIA, where they worked on developing testbench for a co processor cluster, developed testcase infrastructure to re-use the tests written at cluster level for blocks, and worked on developing testbench/testcases for in-house AXI crossbar with UVM methodology. From 2017-2019, they were a Senior Hardware Engineer at Cisco, where they worked on verification of block level testbench for a Flow table cache block, and used fully constrained random stimulus generation by using UVM framework. Lastly, from 2019-present, they are a Verification Manager at Kinara, Inc., where they work on creating different block level and chip level testbenches from scratch, creating scalable test infrastructure to run tests from verification to silicon, and silicon bring up activities and silicon validation.

Venkateshwara Rao completed their M.Tech in VLSI & EMBEDDED SYSTEMS from the International Institute of Information Technology in 2009, having started in 2007.