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Ramesh Reddy P has over 17 years of experience in the electronics and communication fields, currently serving as a Senior Verification Engineer and Senior Verification Lead at Cerium Systems since July 2017. Prior to this role, Ramesh held positions as Senior Tech Lead and Technology Analyst at Synapse Design Inc. from September 2013 to June 2017, and worked at IBM from September 2006 to June 2013 as an R&D Engineer and Functional Verification Engineer. Ramesh holds a PG-Diploma in VLSI from C-DAC (2006) and a Bachelor of Technology in Electronics & Communication from JNTU Anantapur (2001-2005).