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Thejass Chandran is a Senior Principal Design Engineer/Senior Design Engineering Manager with experience in managing teams of ASIC Front End Design Engineers and responsible for RTL design, debug, and enhancements for various projects. With a background in Electronics & Communication engineering, Thejass has a history of working on FPGA-based systems and optimizing performance through micro-architecture design and RTL module integration. Throughout their career, Thejass has demonstrated a strong expertise in leveraging the architectural features of FPGAs to extract the best performance for various applications.