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Sudhir Shetty currently serves as the Design Engineering Group Director at Cadence Design Systems, where responsibilities include establishing and leading a new PHY Frontend Design team focused on LPDDR5X PHY Frontend Design. Prior to this role, Sudhir Shetty was an Engineering Manager at Rambus, successfully initiating a new RTL frontend design team for GDDR6 PHY development and engaging in technical discussions during both pre-sales and post-sales phases. Earlier experience includes serving as a Team Lead at GrowFast Computing Services, contributing to enhancements and maintenance of a Distributed Cash Management System for a leading public sector bank, with a focus on OOPS concepts and relational database systems. Sudhir Shetty holds a Master of Technology degree in Microelectronics from Visvesvaraya Technological University.