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Jos Teunissen is a seasoned Sr. Digital Design/Verification Engineer with extensive experience in the design and verification of complex SoCs across various industries, including audio multiprocessors, automotive, and healthcare technologies. Currently working at Monolithic Power Systems, Inc., Jos specializes in RTL design and verification methodologies, utilizing languages such as VHDL, Verilog, and System Verilog. Previous roles include significant contributions at DatangNXP Semiconductors, NXP Semiconductors, and various technology firms where Jos executed high-level verification projects and led design initiatives. Jos holds a Master's degree in Computer Science from the University of Twente and has a proven track record in mentoring students and driving innovation in digital design.