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Harsh Parikh has strong experience in the field of Design-for-Test (DFT) engineering. They currently hold the position of Principal DFT Engineer at Astera Labs, where they started in November 2022. Prior to this, Harsh worked at AMD from January 2021 to November 2022 as a Member Of Technical Staff. Their earlier work experience includes roles at eInfochips (An Arrow Company), where they served as a Senior DFT Engineer from December 2010 to August 2016, and again from September 2016 to March 2019. They also held the position of Member Of Technical Staff at eInfochips from April 2019 to January 2021.

From 2007 to 2011, Harsh Parikh attended Dharmsinh Desai University, where they earned a Bachelor of Engineering (BE) degree in Electronics and Communications.