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Bryan B. is a seasoned engineer with extensive experience in ASIC design and engineering. Currently serving as a Senior ASIC Design Engineer at ASIC North since February 2013, Bryan specializes in Static Timing Analysis, RTL Design, and Digital Synthesis, along with a focus on mixed signal designs. In a parallel role as Advisory ASIC Design Engineer, Bryan is involved in Memory Subsystem RTL Design and Synthesis. As President of Bullis Investment Group, Bryan oversees an investment firm dedicated to residential properties. Previous roles include Senior Staff Engineer at Qualcomm, where performance enhancements for macro transformations were implemented, and Hardware Engineer at Cisco Systems. Bryan's career began at IBM as a Senior Engineer and earlier as a Programmer at ManTech, where custom accounting systems were developed. Bryan holds a Bachelor of Science degree in Electrical Engineering from Virginia Tech.