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Romain Bouly has extensive work experience in the field of semiconductor engineering. Romain began their career at GIPSA Lab as an intern, where they worked on the validation of a DDR SDRAM interface for a Xilinx FPGA. Romain then joined Sigma Designs as an intern and eventually became an ASIC Design Engineer. In this role, they were involved in various projects, including the design of an Ethernet Gigabit DMA subsystem and the optimization of the RX path of a Gigabit Ethernet DMA subsystem. Since 2011, Romain has been working at Ambarella Inc, initially as an ASIC Verification Engineer and later as a Staff ASIC Verification Engineer. Romain is currently serving as the Principal Verification Engineer.

Romain Bouly obtained a Master's Degree in Electrical Sciences, specializing in Digital Microelectronics design, from ENSERG (National School of Electronics Engineering, Grenoble, France), now known as PHELMA, from 2005 to 2008. Prior to that, from 2003 to 2005, they earned a DEUG (2 year university diploma) in sciences and technology for engineers (electronics, and computer sciences) from the University of Sciences of Montpellier.