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Harinadha Reddy Bodasani is a Senior Engineer at Alphawave Semi since August 2022, with prior experience as an RTL Design Engineer at Cientra from May 2019 to August 2022, where Harinadha developed skills in micro-architecture level IP implementations, RTL writing, debugging, and timing and synthesis processes. Previously, as a VLSI Design Intern at Maven Silicon from June 2018 to May 2019, Harinadha gained knowledge in digital design, Verilog, System Verilog, Universal Verification Methodology, Perl, and assertion-based verification. Harinadha holds a Bachelor of Technology degree in Electronics and Communication Engineering from Aditya College of Engineering, completed in 2018.