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Garret Phillips is an experienced Analog Design Engineer currently working at Aeva since 2021. Prior to this role, Garret held positions as a Mixed Signal Design Engineer at IDEX Biometrics from 2017 to 2021 and as an Analog Design Engineer at Intel Corporation from 2011 to 2017, where responsibilities included designing Multi-Gb Tx/Rx PHYs in the High Speed Serial I/O Group. Earlier experience includes IC design work at Fairchild Semiconductor and Synaptics, as well as various co-op and contractor roles at National Semiconductor and Intel. Garret holds a Master’s degree in Electrical Engineering from Cornell University and a Bachelor of Science in Microelectronic Engineering from Rochester Institute of Technology.