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Sudheer N. is an experienced Physical Design Engineer currently working at Infineon Technologies since April 2022, specializing in Physical Verification for various technology nodes including 130nm, 40nm, 28nm, and 22nm. Responsibilities include full-chip physical verification sign-off checks such as LVS, DRC, soft checks, and latchup, with proficiency in tools like Cadence Virtuoso, Innovus, and Calibre. Additionally, Sudheer N. serves as an ASIC Physical Design Engineer at Quest Global since September 2021 and completed a remote summer internship at IIIT Hyderabad in 2020. Sudheer N. holds a Bachelor of Technology in Electronics and Communication Engineering from Rajiv Gandhi University of Knowledge Technologies, which was completed in 2021.