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Rahul Patil is a Senior Hardware Engineer at ACL Digital since July 2023, with prior experience as a Physical Verification Engineer at Wipro from May 2021 to June 2023. Rahul began their career as an intern at ChipEdge Technologies Pvt Ltd from November 2020 to April 2021, where experience in Physical Design Engineering was gained, focusing on technologies including 28nm and tools such as Synopsys ICC2, Synopsys Primetime, and Synopsys Design Compiler. Key competencies include proficiency in the PD design flow, floor planning, power planning, placement, clock tree synthesis, routing, gate level netlist, and resolving DRC and LVS issues, along with expertise in static timing analysis and scripting languages such as TCL. Prior to this, Rahul completed a training program at Panasonic from September 2019 to February 2020. Educational qualifications include a Bachelor of Engineering in Electrical and Electronics Engineering from KLE Technological University and a Diploma in Electrical and Electronics Engineering from DTE Board Bangalore.