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Filza Shahid is a Design Verification Engineer at 10xEngineers, working on the verification of a RISCV High Performance Out of Order Compute Chiplet project. Previously, Filza served as an Associate Engineer, designing an Asynchronous FIFO memory controller and developing a verification plan for the AHB3-Lite Slave Interface in SystemVerilog. Educational background includes a Bachelor of Applied Science in Electrical and Computer Engineering from the University of Engineering and Technology, Lahore. Additional experience includes a research project focused on H.264 advanced Video Compression, a research internship at York University, and various leadership roles in community and technical organizations, including IEEE Communications Society and IET On Campus UET Lahore.