ÂÜÀòÂÒÂ×

Sudhanshu Tripathi is a Principal Engineer at Western Digital since April 2021, with extensive experience in design and verification roles across various companies. Prior to Western Digital, Sudhanshu held several positions at CircuitSutra from September 2015 to April 2021, including Member of Consulting Staff and SOC Modelling Engineer. Earlier experience includes a role as Design and Verification Engineer at 3ST Technologies, where Sudhanshu worked on MIPI D-PHY and MIPI CSI-2 Rx designs. Sudhanshu also contributed as a Design Engineer at Agnisys Technology, developing DVinsight for System Verilog/UVM, and as an Assistant Trainer at Mentor Graphics, supporting HEP Training programs. With a Master of Technology in Computer Science from Birla Institute of Technology and Science, Pilani, and a B.Tech in Electronics and Communication from Greater Noida Institute of Technology, Sudhanshu possesses strong skills in System Verilog, Verilog, FPGA, and digital system design.