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Stanly Shelly Gomez is a Senior Verification Consultant at Verilab since September 2021, focusing on the verification of a Memory Controller using a 3rd party Coherent Hub Interconnect UVM VIP. Previously, at ams AG from 2009 to August 2021, Stanly served as a Senior Staff Design Verification Engineer, specializing in the design verification of Light Sensor Chips and RTL verification of Sensor ASIC designs with expertise in Verilog, SystemVerilog, and UVM. Initial experience includes roles as a Verification Engineer and Engineering Intern at Texas Advanced Optoelectronic Solutions Inc and a Technical Support Specialist at the School of Economics Policy and Political Sciences. Stanly holds an MSEE in Microelectronic Circuits from The University of Texas at Dallas and a B.Tech in Electronics and Communications Engineering from the University of Kerala.