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Yashodharma Bhat Parthaje is a graduate research assistant and teaching assistant at the University of Minnesota, where education includes a focus on Electronic and Mixed Signal Circuit Design with an expected completion in 2024. Previous experience includes roles as an intern engineer at TDK InvenSense, interim engineering intern at Qualcomm, and analog design engineer at Texas Instruments. Additionally, teaching assistant experience was gained at Arizona State University during the period of 2010 to 2011.