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Atheena Thomas is a seasoned engineering professional with extensive experience in VLSI design and project management. Currently serving as a Lead Engineer at Tessolve since April 2021, Atheena previously held roles as a Senior Layout Engineer at Aricent from December 2017 to April 2021, and as a System Analyst at Reflections - IDEAS MADE REAL from February 2014 to July 2017. Atheena began the career as a VLSI Layout Engineer at NeST Technologies from January 2011 to January 2014, specializing in full-custom IC layout mask design across various CMOS technologies. Atheena holds an Engineer's Degree in Electronics and Communications Engineering from Marian Engineering College and a PG Diploma in VLSI and Embedded Hardware Design from DOEACC Calicut.