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Tim Papenfuss is a seasoned engineering professional specializing in digital design, with extensive experience in ASIC and FPGA development. Currently serving as a Senior Staff Engineer at Synopsys Inc, Papenfuss has previously held significant roles at MicroVision, where contributions included Lead Digital RTL Engineer and Senior Staff Digital RTL Design Engineer. Additional experience includes positions at Artisense Corporation as a Design Engineer focusing on FPGA, and roles at Socionext Europe and Fujitsu Semiconductor Europe GmbH as a Digital Design Engineer.