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John White is a highly experienced Senior Digital Payload Engineer at SWISSto12 since January 2024, with a strong background in FPGA design. Prior to this role, John White served as a Senior FPGA Design Engineer at Ouster from September 2021 to July 2023 and at Capella Space from September 2018 to September 2021. John's expertise in the field also includes a position as a Senior FPGA Design Engineer at RUAG Space from July 2017 to June 2018, and as a Senior ASIC & FPGA Design Engineer at Lockheed Martin from June 2008 to June 2017. John White holds a Bachelor of Science degree in Electrical Engineering and Computer Science from the Rose-Hulman Institute of Technology, earned in 2008.