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Gilles Ries is a highly experienced Senior System Architect at STMicroelectronics, with a career spanning over two decades in hardware design and system architecture for advanced mobile chipsets and SoC development. Since July 2012, Gilles has specialized in optimizing system performance across MCUs, MPUs, and custom SoCs, focusing on architecture setup, DDR controller configuration, and interconnect topology. Prior roles include serving as Senior Principal Engineer and Graphic & Display Architect at ST-Ericsson, where contributions were made to mobile multimedia technologies, as well as positions at STMicroelectronics where involvement included the design of complex hardware blocks and filing several patents. Early career experiences include designing hardware for ADSL/VDSL technologies at Alcatel and creating video decoder chips at Fraunhofer Heinrich Hertz Institute. Gilles holds a Master's degree in Digital Electronics from Télécom Paris and an engineering degree from Université catholique de Louvain.