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Andrew Gouldey is a Senior Principal Engineer at SiFive since February 2021, leading the uncore/interconnect design team and focusing on RTL design for Core SoC/Interconnect. Previously, Andrew served as a Principal RTL design engineer at SiFive, where contributions included designing various IP blocks for PCIe and coherent domain bridging. Prior to SiFive, Andrew spent 16 years at Intel Corporation, concluding as a Senior Staff Engineer responsible for memory technology IP development, with ownership of critical IP logic in high-performance memory controllers. Andrew's career began as a Hardware Engineer at Hewlett-Packard. Academic credentials include a BS and MS in Computer Engineering with a Math minor from Virginia Tech.